ABSTRACT
Silicon complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) continue to achieve increasing levels of integration for digital applications such as microprocessors and high performance application-specific integrated circuits (ASICs). However, manufacturing cost and copper-low-k interconnect delay may constrain future scaling past the 22 nm technology node. In addition, integration of high-performance, highly integrated digital ICs with other technologies such as analog/mixed-signal ICs, imagers, sensors, and wireless transceivers can be limited by packaging technologies, both conventional planar (or 2D) technologies and more recent three-dimensional (3D) stacking. While 3D packaging solutions offer increased functional density, electrical performance and interstrata interconnectivity are limited by wire bonding at the edge of the die. The purpose of 3D integration is to vertically stack and interconnect devices and circuits to form multifunctional, high-performance systems. The various wafer-level 3D technology platforms that have been investigated can be classified as front-end-of-the-line (FEOL) platforms, back-end-of-the-line (BEOL) platforms, and wafer-level packaging (WLP) platforms.
