ABSTRACT

The advent of advanced silicon germanium (SiGe) technologies enabled the implementation of silicon-based wired data communications circuits operating at data rates of 40 Gb/sec and beyond targeting standards such as synchronous optical network (SONET) OC-768. Two key classes of circuits for high data rate communications are serializers, built from a clock multiplying phase locked loop (PLL) and a multiplexer, and deserializers, built from a clock and data recovery PLL and a demultiplexer. The receive subsystem converts the serial optical signal at its input to an electrical format and demultiplexes the resulting serial data stream to create multiple lower speed parallel outputs. The half-rate architecture of the receiver demanded the use of a quadrature voltage control oscillator (VCO). The clock and data recovery (CDR) recovers half-rate quadrature clocks from the input random data stream, using these to recover the incoming 40 Gb/sec data. This chapter considers transmit jitter generation specifications and receive jitter tolerance specifications for the serializer and deserializer circuits.