ABSTRACT
As silicon–germanium (SiGe) processes migrate and lower in cost, opportunities for higher levels of circuit integration and faster signal frequencies arise. In addition, as signal voltage headroom has dropped and circuit noise activity has risen, an urgent need has arisen for accurate understanding and modeling of coupling paths to and from each sensitive part of the circuitry. A key challenge has become the modeling and design of the parasitic effects of the passive devices, integrated circuit package, interconnect, and substrate. Substrate noise has emerged as a real parasitic effect since the mid-1990s. The noise has existed in the silicon substrate for longer, due to digital circuit switching and on-chip oscillators. The chip substrate often offers impedance paths to other points of the circuit and current noise in the substrate results. From the designer’s perspective, the most commonly understood and apparent need for substrate modeling is in the prediction of block-to-block isolation or impedance.
