ABSTRACT
Configurable logic devices have myriad applications. Since their advent in 1985 by Xilinx Corp. [2], FPGAs (Field Programmable Gate Arrays) have advanced significantly. Initially, FPGAs were used primarily for relatively simple applications such as ASIC (Application-Specific Integrated Circuit) prototyping and glue logic. Complex designs were not feasible simply because
5.4.4.1 Logic Cell .......................................................................... 145 5.4.4.2 Routing .............................................................................. 147
5.5 Problems with Previous Architectures ................................................... 147 5.5.1 General Issues ................................................................................. 147
5.5.1.1 Routing Fabric Issues ...................................................... 148 5.5.1.2 New Architecture Proposal ........................................... 149
5.6 RASTER Intercell Communication .......................................................... 150 5.7 RASTER Logic Cell Architecture ............................................................. 152
5.7.1 Logic Cell ......................................................................................... 152 5.7.1.1 Lookup Table .................................................................... 152 5.7.1.2 Fast Ripple Logic ............................................................. 155 5.7.1.3 Fast Feedback Path .......................................................... 155
5.7.2 Routing Architecture ..................................................................... 156 5.7.3 Internal Logic Cell Synchronization ............................................ 157 5.7.4 Internal Pipelining ......................................................................... 158 5.7.5 Power-Up Initialization ................................................................. 159 5.7.6 Implementation Notes.................................................................... 160
5.8 Simulation Results ...................................................................................... 160 5.8.1 Maximum Throughput .................................................................. 160 5.8.2 Area .................................................................................................. 162 5.8.3 Power ............................................................................................... 162
5.9 Benchmarking ............................................................................................. 164 5.9.1 Datapath Design ............................................................................. 165 5.9.2 Synchronous State Machine .......................................................... 166 5.9.3 Asynchronous State Machine ....................................................... 166 5.9.4 Arithmetic Design I ........................................................................ 167 5.9.5 Arithmetic Design II ...................................................................... 168
5.10 Conclusion and Future Research ............................................................. 171 5.10.1 Further Research ............................................................................. 171
5.10.1.1 Power Reduction .............................................................. 171 5.10.1.2 High-Fanout Signals ....................................................... 172 5.10.1.3 Software Place and Route Tools .................................... 173 5.10.1.4 Better Mux Performance ................................................. 173
5.10.2 Potential Uses .................................................................................. 173 5.11 Conclusion ................................................................................................... 174 References ............................................................................................................ 175
the number of logic cells on one chip were on the order of a few hundred. Now, however, transistor density increases have allowed the number of logic cells on a single device to grow to tens of thousands, and speed has increased by orders of magnitude. With this kind of logic density, it is now possible to implement such designs as microprocessors, multimedia accelerators, and data routers. Additionally, it has become commonplace to see ASIC-like blocks, such as large embedded memory, DSPs, high-speed IOs, and processor blocks embedded into FPGA cores. Entire systems-on-a-chip can now be fabricated from one FPGA. Therefore the FPGA itself becomes a critical component in achieving high-speed timing constraints for the system.
