ABSTRACT
This chapter introduces silicon chip implementation trials for Network on Chip (NoC) based System on Chip (SoC's). The implementation and successful measurement demonstrates that high-performance on-chip serialized networking with mesochronous communication is practically feasible. It presents a brief summary of design decisions at each stage, and their rationale on the basis of the low-power consumption of the SoC. The chapter examines the power and area cost of the most popular topologies such as the multilayer bus, 2D-mesh, and the newly proposed hierarchical star (H-star) topology. NoC design can be optimized by the suitable selection of various design parameters, such as queuing buffer size, packet priority assignment, and IP mapping and it provides energy-efficient and performance-optimized communication structures for a large range of applications. The chapter discusses the benefits of the Memory Centric Network On Chip through a comparison with the conventional 2-D mesh topology NoC. It also focuses on the "teraflop of performance" research relating to NOC development and implementation.
