ABSTRACT
Verilog has a profuse set of built-in primitive gates that are used to model nets. The single output of each gate is declared as type wire. The inputs are declared as type wire or as type reg depending on whether they were generated by a structural or behavioral module. This chapter presents a design methodology that is characterized by a low level of abstraction, where the logic hardware is described in terms of gates. Designing logic at this level is similar to designing logic by drawing gate symbols — there is a close correlation between the logic gate symbols and the Verilog built-in primitive gates. Each predefined primitive is declared by a keyword. Chapter 6 through Chapter 9 continue modeling logic units at progressively higher levels of abstraction.
