ABSTRACT
This chapter presents the design time optimization techniques for an optimal dimensioning of the memory hierarchy for low-power operation. It considers a generic system-on-chip memory hierarchy template. In general, the energy consumed by the data memory hierarchy can be optimized for a target template by a careful selection of the set of copy candidates and arrays of the application, and by assigning these to the different layers of the memory hierarchy. In the most general case a cache miss is any transfer of data from main memory to the main memory taking place whenever a load/store operation issues for the data that is not present in the cache. In computer architecture literature, cache misses have been traditionally divided in three categories: compulsory, capacity, and conflict miss types. An optimal replacement strategy uses the capacity of the cache and misses can be avoided because this policy exploits knowledge of the future accesses.
