ABSTRACT
This chapter focuses on the energy/flexibility trade-off for high-performance reconfigurable architectures. It presents the energy efficiency criterion and highlights energy wastes in the reconfigurable design space as well as the opportunities to reduce energy consumption. The chapter also presents the DART architecture implementing energy aware design techniques and innovative reconfiguration schemes. DART is a hierarchical architecture supporting the different levels of parallelism. Each cluster of DART integrates two types of processing primitives: some reconfigurable datapath used for arithmetic processing and an field programmable gate-array core processing data at the bit level. The chapter discusses the implementation results of a key application of next-generation mobile communication systems. It also discusses energy efficiency optimization techniques that can be applied in the case of reconfigurable processors. The chapter considers the significant results stemming from a wideband code division multiple access (WCDMA) receiver implementation on DART. WCDMA is typically considered as one of the most critical applications of next-generation telecommunication systems.
