ABSTRACT
This chapter provides a fundamental power-reduction techniques that can be applied at the structural/micro-architecture level of a complex asynchronous circuit. It focuses on the micro-architecture or structural level of asynchronous circuits. The chapter reviews fabricated asynchronous processors and highlights their performances with respect to low power. It demonstrates that asynchronous processors surpass synchronous processors when designing low-power embedded systems using an operating system based on dynamic voltage scheduling algorithms. The asynchronous bundled-data datapaths are similar to synchronous datapaths consequently all synchronous techniques to reduce power-consumption can be used in the asynchronous design. Some models have been proposed to determine the optimum number of buffers to be added in an asynchronous pipeline to get the maximum throughput. Research in asynchronous logic has lead to interesting circuits that demonstrate the effectiveness of asynchronous logic. The design of Microcontroleur asynchrone was focused on two correlated concerns: designing distributed asynchronous finite state machine and designing for low power.
