ABSTRACT
The power consumption has emerged as a very significant design parameter, which should be taken into consideration by the designer. The field of personal computing devices, wireless communication systems, home entertainment and wearable computers are some from the plethora of the market products, which are becoming increasingly popular. The other hand, physical and technology issues related to chip packaging, cooling, signal integrity, threshold–voltage fluctuations, and variable supply voltages are some challenging problems. The dynamic power dissipation is caused by the charging and discharging of parasitic capacitances in the circuit. The two main low–power reduction strategies concern the reduction of supply voltage and the switched capacitance. The dynamic power consumption is a dominant power component for the current and future design technologies. The circuit techniques based on the principle of parallelism, techniques that use multiple supply voltages and low on-chip voltage swing, and techniques that are circuit technology-dependent and technology–independent.
