ABSTRACT
This chapter describes adiabatic charging, a family of techniques to design logic and other switching circuits which circumvent the lower limit of dynamic power dissipation. The principle of adiabatic charging is wide-reaching — it is grounded in very generic models of the switching elements — but implementations have so far been completely dominated by complementary metal–oxide semi–conductor (CMOS). The conventional, capacitively loaded CMOS inverter depicted. The subproblems must be solved in any realization of the adiabatic–switching principle; an efficient adiabatic logic style that lacks an efficient adiabatic power supply will not provide a low–power solution. The operating power, the ramp signals naturally provide timing information to the circuits, and, therefore, are often referred to as power–clocks or simply as clock signals. This is the motivation for the term “clock–powered circuits”. The adiabatic and energy–recovery techniques offer new possibilities to trade dynamic power dissipation for delay in switching circuits.
