ABSTRACT
The chapter begins by defining nanotechnology and discussing how a metal–oxide–semiconductor field–effect transistor (MOSFET) performs in the nanometer regime, then examines the ultimate scaling limit and practical limits of the silicon MOSFET. The interconnect level, microelectronics uses long, fat wires, but nanoelectronics seeks to use short nanowires. Nanoscale silicon transistors have higher leakage, lower drive current, and exhibit more variability from device to device. The transistor was developed for a very specific purpose — to replace the vacuum tube. In a conventional MOSFET, the channel length is much longer than the electron mean-free-path, so an electron will experience numerous collisions during its travel from the source to the drain. In contrast to the quantum confinement and gate tunneling, quasi-ballistic transport and source-to-drain tunneling begin to significantly affect the device performance of the silicon MOSFET when the gate length scales down to 10 nm or less.
