ABSTRACT
The simple way to distinguish dynamic logic from static logic is to see whether the logic states are correctly maintained, as for the static circuits, or destroyed, as for the dynamic circuits when the clock is turned off. The clocking is used in all synchronous circuits, it is used only as synchronization for static logic circuits while as both synchronization and refreshment for dynamic logic circuits. The true single phase clock (TSPC) circuit technique uses only a single clock and two to three clocked transistors in each latch without local inversion of the clock as such an inversion requires more clocked devices. The strategies of single clock, low count of clocked devices, fewer transistors, nonclassic concept, and simple configurations lead to the results. The latches and flip-flops can be used in a pipeline or a double pipeline. In submicron technologies, the TSPC split-output latches can be used due to reduced threshold voltages.
