ABSTRACT
As SiGe processes migrate and lower in cost, opportunities for higher levels of circuit integration
and faster signal frequencies arise. In addition, as signal voltage headroom has dropped (due to
technology scaling) and circuit ‘‘noise activity’’ has risen (due to higher digital and oscillator frequencies
and higher levels of integration), an urgent need has arisen for accurate understanding and modeling
of the coupling paths to and from each sensitive part of the circuitry. A key challenge has become
the modeling and design of the parasitic effects of the passive devices, IC package, interconnect, and
substrate.
