ABSTRACT
Scaling has driven the entire integrated circuit implementation register transfer level (RTL) to graphic data system II design flow from one which uses primarily standalone synthesis, placement, and routing algorithms to an integrated construction and analysis flow for design closure. This chapter addresses how the challenges of rising interconnect delay led to a new way of thinking about and integrating design closure tools. It describes what drove the design flow from a set of separate design steps to a fully integrated approach, and what further changes we see coming to address the latest challenges. Basic routing, partitioning, and placement algorithms were invented. Partitioning is one of the fundamental steps in the physical design flow. In the implementation era, a design flow could be pasted together from a sequence of discrete steps. High-level synthesis translated a Verilog or VHDL description into an RTL netlist.
