ABSTRACT
This chapter shows how a methodology can be extended to include the effects of package inductance in the analysis. It presents a methodology for the design and analysis of power distribution networks across different stages of the design process. The chapter considers a microprocessor design flow since it includes all aspects of power distribution design and analysis, but the flow applies equally well to any high-performance design. It focuses on the issue of computing the worst voltage drops in the power network. A robust power distribution network is essential to ensure reliable operation of circuits on a chip. Power supply integrity verification is a critical concern in high-performance designs. The enormous size of a power supply network poses difficulty in accurate modeling, simulation, and optimization of power grid. The continued process scaling is likely to make power grid analysis an even more challenging task.
