ABSTRACT
This chapter presents a distinction between designed devices, which are devices that are deliberately created by the designer, and parasitic devices, which were not explicitly intended by the designer but are inherent in the layout of the circuit, and analyzes eight main areas. These are overall system capabilities, designed device extraction, connectivity extraction, parasitic in-line device extraction, parasitic cross-coupled device extraction, and network reduction. The overall design of the extraction system is dictated by the design of the overall system in which it resides. Usually layout extraction is a single component in a much larger system involving a complex database, layout editor, simulator, and design rule checker. The ultimate result of layout extraction will be a circuit description in a form that can be used by a simulator or analysis program. This can be achieved by writing the extracted results out directly as a text file in the simulator language.
