ABSTRACT
As power consumption has become one of the major limiting factors in current electronic systems, this chapter introduces innovative methodologies for successfully dealing with power estimation and optimization during the early stages of the design process. In particular, the presentation offers an insight into state-of-the-art techniques for power estimation at the micro-architectural level, describing how power consumption of components like data-path macros, glue and steering logic, memory macros, buses, interconnect, and clock wires can be efficiently modeled for fast and accurate power estimation. Then, the focus shifts to power optimization, covering the most popular classes of techniques, such as those based on clock-gating, on exploitation of common-case computation, and on threshold and supply voltage management. Ad-hoc optimization solutions for specific components, such as on-chip memories and global buses are also briefly discussed for the sake of completeness.
Most of the aforementioned approaches to micro-architectural power estimation and optimization have now reached a significant level of maturity, and are thus finding their way into commercial CAD tools that are currently hitting the EDA market. Strengths and limitations of the design technology that is at the basis of such tools will be discussed in detail throughout this chapter.
