ABSTRACT
In this chapter, the authors introduce the system-to-register transfer level (RTL) design and verification flow with its objectives and benefits. They focus on the transaction-level model (TLM) view with a description of the modeling style and also discuss the application of these models to support critical activities of platform-based design: early embedded software development, early architecture analysis, and providing a reference model for the functional verification. The authors present how they used the approach in the design of a multimedia multiprocessor platform. A TLM model can replace the manual process undertaken by the verification engineer to generate expected results. Abstraction-level adaptors are required for interfacing TLM and RTL models in this sort of mixed simulation. The system-on-chip (SoC) functional view, as implied by its name, specifies the expected behavior of the circuit perceived by the user. TLM-A is the TLM architecture model that gives an untimed SoC architectural view as presented earlier.
