ABSTRACT
In the previous chapter, machines were synthesized with logic primitives such as, AND, OR, and NOT for both the δ next-state logic and the λ output logic. In this chapter, input and output functions consisting primarily of logic macros such as, multiplexers and decoders will be introduced. Programmable logic devices (PLDs) will be presented as an alternative implementation to further illustrate the synthesis procedure. Microprocessors, which provide considerable flexibility in the design and operation of synchronous sequential machines, will be discussed and their relative merits expounded by means of a design example. Sequential iterative networks such as, shift registers and modulo-n binary counters, will be further investigated and a method established to convert from a combinational iterative network to a functionally equivalent sequential network. The chapter will conclude with a presentation on error detection in synchronous sequential machines.
