ABSTRACT
This chapter discusses technologies used to interconnect embedded processor computing devices. The anatomy of a typical interconnection fabric and some simple topologies are covered. The chapter focuses on the interconnection fabric used for communications between processors in a multiprocessor context and the latter application, drawing heavily on the emerging VME Switched Serial standard as an example. The number and degree of the switches and their interconnection patterns constitute the network topology, which, to a very large extent, determines the scalability of the network. The time it takes a processor to perform a total-exchange operation depends on the bisection bandwidth of the processor. The principal drawback to binary tree switching networks is that the root typically experiences the greatest message traffic. The growth of veryγlarge-scale integration technology has resulted in the availability of crossbar switches of many ports, facilitating the construction of non-binary tree networks.
