ABSTRACT
The proliferation of VLSI circuits has dramatically changed the way electrical test programs are generated. Generating application-specific VLSI circuit test programs has become unmanageably complex. The proliferation of a large number of different configurations requires that an equally enormous number oftest routines be generated, and generated in a short time, rapidly creating a bottleneck. The increased circuit complexity inherent in VLSI devices in terms of both transistor count and circuit function requires an exponential increase in design time-manyears for VLSI circuits versus man-months for SSI!MSI circuits (see Table 8.1). The test program generation of these devices presents as complex and time-consuming a problem as that of circuit design; it must be given equal importance with the design function, and it must be addressed early in the design cycle. Thus, technology is driving test time: the number of devices per chip, the number of external pins, and the cost of the testers themselves. These escalating complexities of chip development have created a number of sophisticated engineering workstations that automate test program generation and tie it to the chip design process via the CAD system. Manual test program generation is no longer viable.
