ABSTRACT

This chapter describes the determination of test patterns for stuck-at faults and introduces the concepts of fault simulation and fault coverage. The testing of a chip is an operation in which the chip-under-test is exercised with carefully selected test patterns. An important problem in testing is test generation, which is the selection of test patterns. The testing of sequential circuits is even more difficult than combinational circuits. Since the response of a sequential circuit is determined by its operating history, a sequence of test patterns rather than a single test pattern would be required to detect the presence of a fault. A fault model represents a subset of the faults that may occur in the chip-under-test. The stuck-open fault model attempts to model the behaviors of a circuit with transistors that are permanently turned off. The transition delay fault model is based on the stuck-at model. Some faults cannot be detected by either the logical fault model/the delay fault model.