ABSTRACT
This chapter covers parallel array processors, which are the single instruction stream, single data stream (SIMD) class of architectures. It revisits the SIMD organization as a means of developing a generic model for this class of architectures. The performance of an SIMD architecture is very much influenced by the data structures used and the memory organization employed. The chapter introduces interconnection networks and provides details of commonly used topologies in SIMD architectures. It also provides performance evaluation concepts and discusses programming considerations. Finally, the chapter describes two SIMD architectures: the ILLIAC-IV an experimental machine for its historical interest and Thinking Machine Corporation’s Connection Machine (CM), a commercial system. One way of minimizing the memory access bottleneck is to include a memory block at the CP in which the instructions reside.
