ABSTRACT

Validation and verification of a system are essential activities throughout the development process: validation checks that we are “building the right system”: that requirements are correctly expressed in a specification, whilst verification checks that we are “building the system right”, that a specification is consistent and internally correct, and that the design meets necessary conditions for termination, confluence and correctness with respect to the specification. In this chapter we describe the validation and verification techniques which are supported by UML-RSDS.