ABSTRACT
In highly scaled three-dimensional technology, the overall performance and reliability of a chip is strongly dependent on the self and coupling parasitics of through silicon vias (TSVs) and interconnects rather than the transistor logic. Therefore, it is essential to reduce the parasitics, and therefore delay and crosstalk, for efficient performance of future high-speed interconnects and TSVs. The performance of any TSV is primarily dependent on the choice of the filler material used. Recently, mixed carbon nanotubes (CNTs) have emerged as an interesting choice for filler material due to their lower thermal expansion, electromigration, higher mechanical stability, thermal conductivity, and current-carrying capability [1-8].
