ABSTRACT
The development of a reliable three-dimensional (3D) integrated system is largely dependent on the choice of liner materials used in through silicon vias (TSVs). Silicon dioxide (SiO2) is the most commonly used liner material for TSVs. The structure of TSVs is composed of Cu, silicon substrate, and silicon dioxide. Due to the large coefficient of thermal expansion (CTE) mismatch of the silicon substrate and Cu high mechanical stress is induced around Cu. This reveals the reliability issues such as high tensile stress, time-dependent dielectric breakdown failure, and drift of Cu atoms. In addition, due to the high relative permittivity of SiO2 liner, the liner capacitance becomes high, which degrades the TSV performance. An improved performance can be obtained for a lower value of liner capacitance [1-6]. The liner capacitance is primarily dependent on the dimensions and dielectric constant of the liner material. The silicon dioxide (SiO2) generates a capacitance of 50 fF-1 pF, with large relative dielectric constant and small thickness (100 nm-1 µm). To reduce the stress effects and liner capacitance offered by SiO2, researchers proposed the low-k dielectric materials as linear materials. Considering these facts, this chapter analyzes the signal integrity for different liner materials such as SiO2, polypropylene carbonate (PPC), benzocyclobutene (BCB), and polyimide. The structure of TSVs with polymer liners is shown in Figure 7.1, in which the dies are stacked in a wedding cake style. Using a pair of single-walled carbon nanotube (SWCNT) bundled TSV, the impact of the liner materials on propagation delay and crosstalkinduced delay is analyzed for different via heights and radii.
