ABSTRACT

This chapter describes the organization of static configuration and dynamic reconfiguration processes at the on-chip level of the reconfigurable computing system. The organization of reconfiguration process which is divided into two parts: reconfiguration of resources at the on-chip level of the field of configurable resource (FCR) and the system level of the FCR reconfiguration. The on-chip configuration static random access memory is usually a 1-bit organized addressable memory unit. The 1-bit organization is dictated by a fine-grained organization of a majority of logic and routing resources in the on-chip FCR. The entire on-chip configuration memory for partially reconfigurable FCR can be organized as 2D array of configuration frames, each of which controls the functionality of the associated resources. The partial reconfiguration is usually initiated by the external configuration controller-loader. As any partial reconfiguration process, self-reconfiguration of the on-chip FCR will require custom internal controller-loader performing all write/read-back operations with partial configuration bit-files.