ABSTRACT

Video Segmentation is indispensable task in any level of video processing. Edge or Gradient image extraction is the starting point in many segmentation algorithms like watershed or Active Contour Model. It is very difficult to perform real time edge detection for high resolution video in general purpose microprocessors. Moreover gradient operator requires square and square root operation which is extremely hardware consuming. To alleviate this problem we have proposed a simple cell network based configurable parallel architecture which performs Morphological gradient detection in few clock cycles. Due to its regular architecture it is also very easy to implement in VLSI. We have implemented the architecture in XILINX VIRTEX II P, FPGA and achieved a 4 clock cycle operations for each morphological operators like dilation and erosion. With a 400 MHz processing clock we have achieved a throughput of 40 MPS (Mega Pixel per Second), which is more than the required real time throughput of PAL standard video. Since most of the core operations in video segmentation can be mapped to morphological operations it can be used as configurable segmentation engine to perform a wide variety of segmentation task.