ABSTRACT
This chapter describes the implementations of all the functional units and peripheral hardware, and presents the hardware schematic diagrams. These diagrams are organized by functional unit. The chapter presents the detailed hardware design of the system. The system's processing elements are designed specifically to execute rules efficiently and to meet the requirements of real-time expert systems. Special purpose hardware is used to implement the functions performed by the Active Rule List (ARL). The control of the ARL hardware is performed by Advanced Micro Devices' PROSE sequencers. The two memories in the ARL are the Rule Memory (RM) and the Active Rule List Memory (ARLM). The RM is a 4K by 32 bit memory implemented using TMS27C49 EPROM. The Antecedent Priority Queue stores antecedent data from the ARL into one of 16 separately maintained queues.
