ABSTRACT
This chapter focuses on chip-level solutions in mixed-criticality systems, which are categorized in memory and network bandwidth regulations, and addresses interleaving and support for mixedcriticality at the network on chip level. It draws on the architecture and evaluation of the hardware MemGuard, and addresses interleaving at the NoC-level. Genuine MemGuard allows sharing guaranteed bandwidth over several cores using a dynamic reclaim mechanism. The genuine MemGuard algorithm targets the average bandwidth instead of peak bandwidth reservation, which limits its use in real-time applications. Multi-Processor Systems-on-a-Chip offer tremendous potential in embedded systems, due to combining computational capacity and energy efficiency. The data area is implemented by a memory that stores the messages. Based on the direction of the port, the memory is either written to or read from by a driver at the application layer. Each port is configured by a set of parameters, a part of which can be updated at run-time.
