ABSTRACT
Chapter 2, “Circuit Level Testing,” describes various circuit level techniques to reduce temperature. Reordering the test vectors has been shown to be a potential avenue to reduce temperature. As test pattern generation tools leave a large number of bits as don't cares, they can be filled up conveniently to aid in temperature reduction. Usage of different types of flip-flops in the scan chains can limit the activities in different portions of the circuit, thus reducing heat generation. Built-in-self-test (BIST) strategies use an on-chip test pattern generator and response analyzer. These modules can be tuned to get a better temperature profile. Associated techniques, along with experimental results, are presented in this chapter.
