ABSTRACT
This chapter presents a software and hardware codesign flow for FPGAbased coarse-grained architectures. A novel multi-target design space exploration (MT-DSE) method is employed in the flow to help designers find the most effective trade-off architecture. Without the time-consuming simulations or implementations, this lightweight MT-DSE method only needs some early stage profile information; after that, a well-optimized scheme would be reported to the designers. System designers could benefit a lot from MT-DSE, as in recent years the requirement for time-to-market has become more and more demanding.
