ABSTRACT
Each of the memory storage cells which comprise the first basic block of the static memory, consists of two inverters connected in back-to-back formation and an accessing circuitry to these inverters. The Rapid Read-Write Static Memory technique is working in this direction as its fast operations allow the transfer of the demanded data to the functioning units quicker. The block diagram of the single-paged conventional Static random-access memory (SRAM) model has been extended in order to support the enhancements of the Rapid Read-Write SRAM model. At the Read operation of the Rapid SRAM, the new Bit Line Pre-charger that the Rapid SRAM makes use of has already pre-charged the BL and BLB wirelines to a suitable voltage level for the memory, before the Write operation starts. The Rapid SRAM 6T transistor is in the data retain operation state when the word line signal is switched off.
