ABSTRACT
Adherence to Moore's law is arguably the key technological and economic driver for the nanoelectronics industry. Geometric transistor scaling enabled process manufacturing technology to keep pace with Moore’s law until the early 2000s, when it was realized that disruptive enhancements beyond geometric scaling would need to be implemented. One key innovation was the introduction of strain enhancements into the transistor architecture. This development
necessitated the requirement for the measurement of transistor strain and also the characterization of various stressor systems. This chapter reviews the fundamental aspects of strain with transistor device performance and the key analytical developments that have filled this critical capability gap. Various analytical methods are reviewed, each with unique strengths in providing a range of capabilities that include fundamental characterization, rapid analysis, and measurements at the device, die, and wafer levels. We also examine the scalability and versatility of these analytical methods as they will be needed to provide a path for future strain engineering programs with a new class of emerging transistor material and architectural options.
