ABSTRACT
This chapter introduces the dual-k spacer concept that uses an optimal high-k spacer length for enhancing the device performance of an underlap FinFET. Spacer engineering plays a significant role in describing the electrostatics and charge dynamics of the underlap devices. Current characteristics and short-channel effects (SCEs) metrics of the proposed symmetric and asymmetric dual-k spacer devices are presented and compared with conventional single/low-k as well as purely high-k FinFET structures. The optimized symmetric dual-k spacer architecture, abbreviated as "SymD-k", consists of an inner high-k and an outer low-k spacers on both source and drain sides. For the SymD-k FinFET, the drive current increases 2.4* with an off-state leakage current (IOFF) reduction of nearly 77" as compared with the conventional one. The chapter discusses the performance evaluation of the FinFET devices using parameters such as drive current, gate leakage current, subthreshold current, and short-channel parameters.
