ABSTRACT
This chapter focuses on selected stack-design consideration for enhancement of the first group of device parameters not only from application enhancement for conventional nonvolatile memories (NVMs) but also from the standpoint of device concepts leading to SUM devices. It also focuses on device concepts applicable to split-gate CT-NVMs of advanced planar and quasi-planar and trench-based vertical channel configurations to address the requirements of all NROM segments outlined in. The chapter addresses the key future application drivers for silicon based embedded and stand-alone NVM devices from device design perspectives and propose cost-effective future device concepts to: maintain and expand application horizon against the scaling challenges and limitations being faced through current approaches; and effectively compete against emerging "non-silicon" contenders such as MRAM and RRAM. Consequently, the NVM devices and technology features need to be compatible with the Bulk or SOI logic platform and would require minimal additional process complexity to satisfy cost/performance/power objectives.
