ABSTRACT

This chapter summarizes logic design styles, stressing low power design issues. It describes new and emerging logic styles for specialized libraries. The chapter also describes some of these logic families, which are assumably the most interesting regarding low–power designs. The design of a complementary metal oxide semiconductor gate is generally performed by synthesizing the N–ch network by taking the “0” cubes in the Karnaugh map of the Boolean function. The separated simplification method has been introduces in order to be capable of having the two N–ch and P–ch expressions as sums of products. The “branch–based logic”, logic cells are designed exclusively with branches composed of transistors in series connected between a supply line and the gate output. The main advantage of such an implementation is the layout density. The standard cell libraries often provide a huge number of cells, up to 300 or even 500. The deep submicron technology, robustness is the main challenge after low power consumption.