ABSTRACT
This chapter aims to provide front–end designers with guidelines and good design practices for writing efficient register transfer logic (RTL) code from a low–power standpoint. The RTL–level techniques are very efficient because hardware description language (HDL) programmers are knowledgeable about the circuit architecture and functionality. The RTL synthesis has been a major improvement in the field of digital integrated circuit design. The static power consumption is due to metal oxide semiconductor sub–threshold leakage and to a lesser degree extends to gate–induced drain leakage, gate leakage, and diode leakage. The design for low power might require a very predictable and reproducible synthesis mapping. A generic component name should be used in the architecture part of the very high speed HDL code. The clock–gating file and the register file must be physically close to reduce the impact on the skew and to prevent unwanted optimizations during the synthesis phase. The source of consumption and each type of digital block, appropriate solutions implemented.
