ABSTRACT
This chapter presents deep inside register transfer level (RTL) power modelling and provides a detailed insight to the different facets of the problem of building accurate, yet efficient and easy to characterize RTL power models. The problem of power estimation at the RTL amounts to building a power model that relates the power consumption of the target design to suitable quantities. The scientific contributions on RTL power modeling assume an architectural template that views an RTL design as the interaction of a datapath and a controller, which fits well the so–called finite state machine with datapath model. A number of articles dealing with power macro–models have appeared in the literature. The ability of accurately characterizing power consumption of complex digital components is at the basis of the setup of power estimation capabilities usable at high levels of abstraction.
