ABSTRACT
This chapter describes the fundamental architecture of the Intel math units and its math unit instruction set. Intel math units have many common elements in their internal architecture. Structurally, the math units are divided into a control unit (CU) and a numeric execution unit (NEU). Usually, these structures are invisible to the programmer, who perceives the math unit as consisting of the addressable data areas and a dedicated instruction set. The numeric execution unit of the FPU contains eight internal registers for operational data. Many instructions allow these registers to be addressed explicitly, that is, according to their designation in the ST(i) form. The math unit’s internal structure for holding operational data can be viewed as a stack-like arrangement of eight individually addressable units. Each register stores a binary real number in extended precision format. The values inside rectangles represent the register’s physical number. The ST(i) designation, shown inscribed in circles, indicates the register’s relative position in the stack.
