ABSTRACT
Annular Pull-Down Transistors (Type 4) .......................... 163 7.4 SNM Test Structure ...................................................................................... 164 7.5 Experimental TID Testing Results ............................................................... 164
7.5.1 Impact of VDD Bias on TID Response ............................................... 166 7.5.2 Impact of TID on Cell Margins ........................................................ 167 7.5.3 Type 4 Cell ........................................................................................ 170 7.5.4 Type 1 Cell with RBB-Array Design Considerations .................... 170 7.5.5 Type 1 Cell with RBB-Transistor Level Measurements ................ 172 7.5.6 Test SRAM Designs and Experiments ............................................. 172 7.5.7 Type 1 Cell with RBB-SRAM Measurements .............................. 173 7.5.8 90 nm Transistor-Level Response ..................................................... 177
7.6 Single-Event Effects in Unhardened SRAM ................................................ 177
Static random access memory (SRAM) is ubiquitous in modern system-on-a-chip (SOC) integrated circuits (ICs). Due to its value in programmable systems by providing fast scratchpad memory in embedded and real-time applications as well as space for large working sets in microprocessor designs, IC SRAM content continues to grow. As ICs surpass 1 billion transistors, and given the high relative design and power efciency of memory arrays compared with random logic, SRAM is projected to comprise 90% of the total die area by 2013 [1]. For instance, the Itanium processor has progressed from 6 MB and 9 MB L3 caches on 130 nm fabrication processes to 24 MB caches on the 65 nm technology generation [2-4]. The Xeon processors include 16 MB caches [5]. Consequently, ICs designed for space and other radiation environments require robust SRAM designs if they are to track the size and performance of commercial ICs.
