ABSTRACT
Experiments ......................................................................................205 8.3.4 MCU as a Function of Technology Feature Size ..............................205 8.3.5 MCU as a Function of Design: Well Tie Density .............................205 8.3.6 MCU as a Function of Supply Voltage .............................................207 8.3.7 MCU as a Function of Temperature .................................................207 8.3.8 MCU as a Function of Bit Cell Architecture ....................................207 8.3.9 MCU as a Function of Test Location LANSCE versus
TRIUMF ...........................................................................................208 8.3.10 MCU as a Function of Substrate: Bulk versus SOI ..........................209 8.3.11 MCU as a Function of Test Pattern................................................... 210
8.4 3-D TCAD Modeling of MCU Occurrence ................................................. 210 8.4.1 Bipolar Effect in Technologies with Triple Well .............................. 212
Susceptibility to radiation environment of advanced electronic devices is often responsible for the highest failure rate of all reliability concerns (e.g., electromigration, gate rupture, negative bias-temperature instability [NBTI]). In modern static random access memories (SRAMs) the two predominant single-event effects (SEEs) are the single-event upset (SEU) and multiple upsets (MUs). Multiple upsets are topological errors in neighboring cells. If the cells belong to the same logical word they are named multiple-bit upsets (MBUs); otherwise they are labeled as multiple-cell upsets (MCUs). Multiple upsets have received increased scrutiny in recent years [1-8] because MBUs are uncorrectable by a simple error correction code (ECC) scheme and therefore threaten the efciency of error detection and correction (EDAC).
