ABSTRACT
This chapter presents circuit topology-based test pattern generation for small-delay defects (SDDs). The circuit topology-based method leads to only a small increase in the pattern count and provides high coverage of gross-delay defects and SDDs. Because only a fraction of faults is considered for timing-aware automatic test pattern generation (ATPG), the circuit topology-based SDD pattern generation method also results in runtime savings. The chapter also presents detailed experimental results for several International Workshop for Logic Synthesis (IWLS) benchmarks to show the effectiveness of the proposed method. It compares the test quality and pattern effectiveness based on several different metrics: delay test coverage as reported by ATPG, total number of long paths excited by the pattern set, length of the longest path excited by the pattern set, and number of unique SDD locations covered by the pattern set. The chapter also discusses the defective parts per million impact of the proposed method in terms of detecting randomly injected SDDs.
