ABSTRACT
This chapter discusses the effects of sample size, grain boundaries, and surface morphology on the thermoelectric behavior of semiconductor nanowires (NW) are addressed with particular focus on Silicon (Si) NWs, which are pertinent for power generation in microscale- and nanoscale-integrated devices. It describes the conventional atomic-scale simulation techniques for computing thermal conductivities in NWs. The chapter provides an overview of size effects on thermal conductivity of Si NWs with or without a native oxide layer. It addresses the roles played by grain boundary superlattices and surface morphology on nanoscale heat transport. The chapter presents a discussion on the effects of sawtooth surface faceting and alloy scattering on thermal conductivity in Si-based NWs, which opens up new opportunities for future research in nanoscale thermoelectrics. Intense research efforts have been devoted to understanding how surfaces and interfaces influence properties at the nanoscale level in crystalline nanowires from semiconductors and metals.
