ABSTRACT

In modern deep submicron chip design, power distribution and clock generation and distribution are the two essential issues that determine whether the chip may be successful on the market or not. For a system to be workable, each part of the logic module must be powered through a power distribution network and driven by a clock distribution network. The objective of the power distribution network is to evenly distribute the power supply to all individual devices in the system in an undisturbed fashion. We begin in this chapter with the introduction of the design issues of power distribution networks and then discuss power distribution networks. In addition, the decoupling capacitors and their related issues are discussed.