ABSTRACT
The choice of multiprocessor organization and interconnect has a significant impact on how the cache coherence protocol should be designed. Cache coherence protocol choice must support the scale of the system, which is affected by the organization. Supporting scalability is expensive, thus a cache coherence protocol should not be over-designed. This chapter discusses basic issues when designing cache coherence protocols. Despite having the seemingly simple objectives of ensuring a consistent view of cached values through write propagation and transaction serialization, there is a wide range of design choices for implementing a cache coherence protocol. The chapter describes the write invalidate strategy, and discuss different protocols that rely on this strategy. The protocols are described in increasing sophistication, and one builds upon another. More sophisticated protocols use less bandwidth but are more complex to implement. Readers are advised to read the protocols sequentially. The chapter also discusses one write update coherence protocol and provides comparison between broadcast and directory protocols.
