ABSTRACT
This chapter discusses the memory consistency problem in more detail, what solutions are offered in current systems, and how they relate to performance. It begins the discussion with programmers’ intuition regarding the ordering of memory accesses. The chapter shows that they in general conform to full ordering of memory accesses, and the model that corresponds to such ordering requirements is referred to as the sequential consistency (SC) model. It also shows how SC can be provided in a multiprocessor system and which parts of the processor or coherence protocol mechanisms must be changed. The chapter also discusses that such changes are too restrictive and likely produce a high performance overhead. As a result, many processors do not implement SC. Rather, they implement more relaxed consistency models, such as processor consistency, weak ordering, and release consistency. The chapter considers each of them and show how performance is impacted by different consistency models.
