ABSTRACT
This chapter reviews the major issues facing conventional complementary metal–oxide–semiconductor (CMOS) scaling. It also discusses the basics of a fully depleted device operation and fully depleted devices overcome the barriers that limit conventional scaling. Gate-length scaling for fully depleted devices* is governed by fundamentally different principles compared with conventional transistors. While gate dielectric scaling, extension, and halo engineering are all somewhat useful, it is the body thickness that is the strongest parameter in gate-length scaling for fully depleted devices. Increasing the gate length is another approach that was extensively used in conventional CMOS. Conventional scaling is nearing its limits due to the lack of gate dielectric scaling and also the ineffectiveness of channel doping at high halo doses. Scalability is another key question for any device architecture. Typically, there is a significant investment in design infrastructure and yield learning for any particular device architecture. New device architectures are needed to continue the scaling trend.
