ABSTRACT
This chapter presents the encoder and decoder architectures for Binary Bose-Chaudhuri-Hocquenghem (BCH) codes. It explains the implementation architectures for soft-decision Chase BCH decoders. BCH codes are also constructed by making use of finite fields. BCH encoder can be implemented by a linear feedback shift register architecture. BCH codes whose codeword length is thousands of bits are used in the Digital Video Broadcasting Standard and Flash memories. In addition, very long BCH codes perform better than Reed-Solomon codes of similar code rate and codeword length over the additive white Gaussian noise channel. BCH codes can achieve very high throughput with simple hardware implementations, and hence have been considered for applications such as computer memories and optical communications. BCH codes constructed over high-order finite fields, additional approaches are available to further reduce the decoding complexity. The interpolation-based decoding was originally developed based on the interpretation that the codeword symbols are evaluation values of the message polynomial over finite field elements.
